1. Field of the Invention
The invention relates to a method for the computer-controlled generation of pulse intervals with periods of repeating pulse intervals.
2. Background Art
A method of this type is disclosed, for example, in German Patent No. 27 46 743 commonly owned by the applicant.
The essential feature of the method described in the aforementioned patent is that no dead times occur between the pulse intervals to be generated. The length of the pulse intervals is determined by a decrementer. Before the decrement procedure is run (i.e. before status "0" is reached) the decrementer is loaded with a new value (for the next pulse cycle), so that the new decrement procedure follows on from the previous one immediately.
A processor is generally used in implementing this procedure. Most processors operate on the "von Neumann principle": a controller is supplied with instructions contained in a (program) buffer for execution. Once an instruction has been executed, the processor turns to the next address in the program buffer where the next instruction is stored, and so on.
The cycle time of the processor in high speed computers is determined by the storage access time and by the controller unit processing time in equal measure.
The generation of pulse interval sequences, particularly for the purposes of testing high-speed storage units and logic circuits, requires the generation of extremely short pulse intervals (in which the test pulses may be placed).
According to the state of the art, there are test systems, as illustrated in FIG. 3, which incorporate sub-storages 81, 82, and 83 in addition to a main processor 80 with a central storage. The main processor 80 is connected both directly and through a sub-storage to an address generator (84), data generator (85) and clock pulse generator (86) which, for their part, are connected to a circuit 87 generating pulse interval sequences.
The sub-storages hold various special instruction sequences. The generator circuit 84, 85 and 86 obtains its information on the one hand directly from the central storage (general data, e.g. program start addresses, start, stop) and on the other hand (special data, e.g. pulse time relation, interval time, ALU Opcodes (ALU=arithmetic and logical unit)) from the appropriate sub-storages. The provision of sub-storages with various different, special instruction sequences gives a significant advantage from the point of view of programming: the various instruction sequences in the sub-storages may easily be combined together.
In this context it should, however, be mentioned that the intermediate circuit of a sub-storage causes a further time overhead.